There is a demand to increase transmission speed with respect to signal transmission between circuit blocks within a chip, signal transmission between LSI chips, and/or signal transmission between boards and/or housings. In order to increase signal transmission speed, clock and bias signals applied to an input and output circuit that inputs and outputs transmission signals may need to be optimized.
For the purpose of attaining high-speed operation, generally, a clock signal having small amplitude that entails a small dead time is desirable. When generating a small-amplitude clock signal, the center voltage and amplitude may need to be adjusted to proper values to avoid unstable circuit operations. The use of insufficiently small clock signal amplitude, for example, may give rise to a problem in that the circuit is not operational.
FIG. 1 is a drawing illustrating an example of the configuration of a related-art circuit for adjusting to an optimum value the center voltage of a clock signal input into an input and output circuit. A circuit of FIG. 1 includes an input and output circuit 10, a waveform detecting circuit 11, a waveform comparing circuit 12, an adjustment circuit 13, a clock buffer 14, and an ideal waveform generating circuit 15. This circuit is disclosed in Patent Document 1.
The clock buffer 14 is configured to adjust the center voltage of a clock signal clk that is output therefrom. The input and output circuit 10 receives data signal “data” in response to the clock signal clk supplied from the clock buffer 14, and outputs the received data signal “data”.
The waveform detecting circuit 11 detects the center voltage of the clock signal clk supplied to the input and output circuit 10. The ideal waveform generating circuit 15 generates a reference voltage equal to the center voltage of a clock signal clk that is expected to cause the circuit to properly operate. The waveform comparing circuit 12 calculates a difference between the reference voltage and the center voltage of the clock signal detected by the waveform detecting circuit 11, and supplies a signal indicative of this difference to the adjustment circuit 13. In response to the difference indicated by the received signal, the adjustment circuit 13 adjusts operating parameters of the clock buffer 14 to perform such feedback control that the difference becomes zero. This feedback control ensures that the input and output circuit 10 receives a clock signal clk that has a proper center voltage.
In the configuration described above, however, there is no guarantee that the input and output circuit 10 properly operates with absolute certainty even if a clock signal clk having the same center voltage as the reference voltage generated by the ideal waveform generating circuit 15 is supplied to the input and output circuit 10. For example, the input and output circuit 10 may have manufacturing variation, so that the center voltage of its optimum clock signal may be different from the expected voltage. Even if there is no manufacturing variation with respect to the input and output circuit 10, manufacturing variation in the ideal waveform generating circuit 15 may cause an error in the reference voltage, resulting in an operation failure.
In consideration of this, provision may be made to detect the output of the input and output circuit 10 to check the operation of the input and output circuit 10. In such a case, it is easy to check the operation of the input and output circuit 10 if the input/output signal “data” of the input and output circuit 10 is a periodic signal that exhibits regular transitions such as a clock signal. However, the input/output signal “data” of the input and output circuit 10 may be an ordinary data signal. It is then not guaranteed that this signal output exhibits a transition within a predetermined time period. It is thus not possible to check, solely based on the signal output, whether the input and output circuit 10 is properly operating.    [Patent Document 1] Japanese Patent Application Publication No. 2004-172980